Verilog有限状态机(2)

HDLBits链接

前言

继续更新状态机小节的习题。

题库

题目描述6：

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Solution6：

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module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = (state[A]&~in) | (state[C] & ~in);
    assign next_state[B] = (state[A]&in) | (state[D]&in) | (state[B]&in);
    assign next_state[C] = (state[B]&~in) | (state[D]&~in);
    assign next_state[D] = (state[C]&in);

    // Output logic: 
    assign out = (state[D]);

endmodule

本题中作者想让我们以one-hot(独热码)的编码逻辑来完成。一般状态机为了方便编码都是设置为二进制；但若状态转移是按顺序进行转移的话，我们可以使用格雷码，因为两相邻状态之间只变化1bit，这样可以节约功耗；若想提升速度，可以使用one-hot编码，因为每次仅需判断一位，这是用寄存器资源换组合逻辑资源，以达到更高的速度。

题目描述7：

题目与上题相同，区别为异步复位，复位至状态A。

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Solution7：

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module top_module(
    input clk,
    input in,
    input areset,
    output out); //

    parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;
    reg [1:0] state,next_state;
    
    always @(*)begin
        case(state)
            A:begin
                if(in == 0)begin
                    next_state = A;
                end
                else begin
                    next_state = B;
                end
            end
            B:begin
            	if(in == 0)begin
                    next_state = C;
                end
                else begin
                    next_state = B;
                end
            end
            C:begin
            	if(in == 0)begin
                    next_state = A;
                end
                else begin
                    next_state = D;
                end
            end
            D:begin
                if(in == 0)begin
                    next_state = C;
                end
                else begin
                    next_state = B;
                end
            end
        endcase
    end

    always @(posedge clk,posedge areset)begin
        if(areset)begin
            state <= A;
        end
        else begin
            state <= next_state;
        end
    end

    assign out = (state == D);

endmodule

题目描述8：

题目同上题，将复位改为同步复位。

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Solution8：

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module top_module(
    input clk,
    input in,
    input reset,
    output out); //

parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3;
    reg [1:0] state,next_state;
    
    always @(*)begin
        case(state)
            A:begin
                if(in == 0)begin
                    next_state = A;
                end
                else begin
                    next_state = B;
                end
            end
            B:begin
            	if(in == 0)begin
                    next_state = C;
                end
                else begin
                    next_state = B;
                end
            end
            C:begin
            	if(in == 0)begin
                    next_state = A;
                end
                else begin
                    next_state = D;
                end
            end
            D:begin
                if(in == 0)begin
                    next_state = C;
                end
                else begin
                    next_state = B;
                end
            end
        endcase
    end

    always @(posedge clk)begin
        if(reset)begin
            state <= A;
        end
        else begin
            state <= next_state;
        end
    end

    assign out = (state == D);

endmodule

题目描述9：

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Solution9：

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module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    
    parameter A2=3'd0,B1=3'd1,B2=3'd2,C1=3'd3,C2=3'd4,D1=3'd5;
    reg [2:0] state,next_state;
    
    always @(*)begin
        case(state)
            A2:next_state = s[1]?B1:A2;
            B1:next_state = s[2]?C1:(s[1]?B1:A2);
            B2:next_state = s[2]?C1:(s[1]?B2:A2);
            C1:next_state = s[3]?D1:(s[2]?C1:B2);
            C2:next_state = s[3]?D1:(s[2]?C2:B2);
            D1:next_state = s[3]?D1:C2;
            default:next_state = 'x;
        endcase
    end
    
    always @(posedge clk)begin
        if(reset)begin
        	state <= A2;
        end
        else begin
        	state <= next_state;
        end
    end
    
    always @(*)begin
        case(state)
            A2:{fr3,fr2,fr1,dfr} = 4'b1111;
            B1:{fr3,fr2,fr1,dfr} = 4'b0110;
            B2:{fr3,fr2,fr1,dfr} = 4'b0111;
            C1:{fr3,fr2,fr1,dfr} = 4'b0010;
            C2:{fr3,fr2,fr1,dfr} = 4'b0011;
            D1:{fr3,fr2,fr1,dfr} = 4'b0000;
            default:{fr3,fr2,fr1,dfr} = 'x;
        endcase
    end

endmodule

小结

今天先更新这几道题目，重点是one-hot编码部分，了解其与格雷码的优缺点。