HDLBits答案汇总

前言

该博客为本人做HDLBits习题时的心得记录总结，欢迎大家一起交流进步。

HDLBits网站链接

Verilog Language

Basics_Verilog%E8%AF%AD%E6%B3%95%E5%9F%BA%E7%A1%80/)

Vectors_Verilog%E5%90%91%E9%87%8F%E5%9F%BA%E7%A1%80/)

Modules:Hierarchy_Verilog%E6%A8%A1%E5%9D%97%E7%9A%84%E4%BE%8B%E5%8C%96%E4%B8%8E%E8%B0%83%E7%94%A8/)

Procedures_%E5%A6%82%E4%BD%95%E9%81%BF%E5%85%8D%E7%94%9F%E6%88%90%E9%94%81%E5%AD%98%E5%99%A8/)

More Verilog Features_Generate%E5%AE%9E%E4%BE%8B%E5%8C%96%E6%A8%A1%E5%9D%97/)

Circuits

Combinational Logic

Basic gates_%E7%A1%AC%E4%BB%B6%E6%A8%A1%E5%9D%97%E8%AE%BE%E8%AE%A1%E7%9A%84%E6%80%9D%E8%80%83%E6%96%B9%E5%BC%8F/)

Multiplexers_Verilog%E5%A4%9A%E8%B7%AF%E9%80%89%E6%8B%A9%E5%99%A8/)

Arithmetic Circuits_Verilog%E5%8D%8A%E5%8A%A0%E5%99%A8%E3%80%81%E5%85%A8%E5%8A%A0%E5%99%A8%E5%92%8C%E8%A1%8C%E6%B3%A2%E8%BF%9B%E4%BD%8D%E5%8A%A0%E6%B3%95%E5%99%A8%E5%8E%9F%E7%90%86%E4%B8%8E%E8%AE%BE%E8%AE%A1/)

Karnaugh Map to Circuit_%E5%8D%A1%E8%AF%BA%E5%9B%BE%E4%B8%8E%E6%9C%80%E7%AE%80SOP%E5%BC%8F/)

Sequential Logic

Latches and Flip-Flops_D%E8%A7%A6%E5%8F%91%E5%99%A8%E3%80%81%E5%90%8C%E6%AD%A5%E4%B8%8E%E5%BC%82%E6%AD%A5%E5%A4%8D%E4%BD%8D%E3%80%81%E8%84%89%E5%86%B2%E8%BE%B9%E6%B2%BF%E6%A3%80%E6%B5%8B/)

Counters_Verilog%E8%AE%A1%E6%95%B0%E5%99%A8/)

Shift Registers_Verilog%E7%A7%BB%E4%BD%8D%E5%AF%84%E5%AD%98%E5%99%A8/)

More Circuits_Verilog%E7%A7%BB%E4%BD%8D%E5%AF%84%E5%AD%98%E5%99%A8%E9%99%84%E5%8A%A0%E9%A2%98/)

Finite State Machines

Simple FSM 1—Simple state transitions 3_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(1)/)

Simple one-hot state transitions 3—Design a Moore FSM_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(2)/)

Lemmings 1-4_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(3)/)

One-hot FSM—PS/2 packet parser and datapath_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(4)/)

Serial receiver—Serial receiver with parity checking_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(5)/)

Q8—Q5b_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(6)/)

Q3a—Q6_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(7)/)

Q2a—Q2b_Verilog%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA(8)/)

Building Larger Circuits_%E5%9F%BA%E4%BA%8E%E6%9C%89%E9%99%90%E7%8A%B6%E6%80%81%E6%9C%BA%E7%9A%84%E8%AE%A1%E6%95%B0%E5%99%A8/)

Verification:Reading Simulations

Finding bugs in code_%E6%89%BEBUG/)

Build a circuit from a simulation waveform_%E7%94%B1%E6%B3%A2%E5%BD%A2%E5%9B%BE%E6%8F%8F%E8%BF%B0%E7%94%B5%E8%B7%AF/)

Verification:Writing Testbenches_%E7%BC%96%E5%86%99Testbench/)