前言

该博客为笔者做HDLBits习题时的心得记录总结，欢迎大家一起交流进步。

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Verilog Language

Basics_Verilog语法基础/)

Vectors_Verilog向量基础/)

Modules:Hierarchy_Verilog模块的例化与调用/)

Procedures_如何避免生成锁存器/)

More Verilog Features_Generate实例化模块/)

Circuits

Combinational Logic

Basic gates_硬件模块设计的思考方式/)

Multiplexers_Verilog多路选择器/)

Arithmetic Circuits_Verilog半加器、全加器和行波进位加法器原理与设计/)

Karnaugh Map to Circuit_卡诺图与最简SOP式/)

Sequential Logic

Latches and Flip-Flops_D触发器、同步与异步复位、脉冲边沿检测/)

Counters_Verilog计数器/)

Shift Registers_Verilog移位寄存器/)

More Circuits_Verilog移位寄存器附加题/)

Finite State Machines

Simple FSM 1—Simple state transitions 3_Verilog有限状态机(1)/)

Simple one-hot state transitions 3—Design a Moore FSM_Verilog有限状态机(2)/)

Lemmings 1-4_Verilog有限状态机(3)/)

One-hot FSM—PS/2 packet parser and datapath_Verilog有限状态机(4)/)

Serial receiver—Serial receiver with parity checking_Verilog有限状态机(5)/)

Q8—Q5b_Verilog有限状态机(6)/)

Q3a—Q6_Verilog有限状态机(7)/)

Q2a—Q2b_Verilog有限状态机(8)/)

Building Larger Circuits_基于有限状态机的计数器/)

Verification:Reading Simulations

Finding bugs in code_找BUG/)

Build a circuit from a simulation waveform_由波形图描述电路/)

Verification:Writing Testbenches_编写Testbench/)